This article is part of TechXchange: RISC V
Lattice semiconductor is well known for its FPGAs. Usually developers add their own firmware, but the company’s new Lattice Automate provides a more complete solution that integrates artificial intelligence / machine learning (AI / ML) with motor control.
Lattice Automate targets a range of Lattice FPGAs with a framework that includes a flexible core RISC-V processor, convolutional neural network (CNN) accelerator, and motor control with Ethernet support (Fig. 1). The system can use any number of feedback systems such as Hall effect or current sensors. It can also work in a sensorless environment.
Likewise, Lattice Automate is capable of controlling multiple motors using different drive systems. Predictive maintenance models and application code that can be customized and extended are included. A host-based GUI interface is available for system monitoring and control.
More complex systems require distributed motor control. Lattice’s EtherConnect technology is designed to connect multiple FPGAs using low-overload Ethernet-type communication (Fig. 2). Connections can be made in daisy-chain as well as star configurations. The protocol and signaling are essentially the same but allow the use of non-standard interfaces.
Real-time communication provides a way to synchronize motor control across the network. Protocol stacks are provided for the RISC-V core. Additionally, a conventional Ethernet interface can be included to provide a gateway.[SESB:664823]
Lattice FPGAs implement a hardware root of trust that can be leveraged by the RISC-V core. In terms of system configuration, Lattice Propel v2.0 allows a developer to combine functionality at the block level instead of the more precise, albeit detailed, Lattice Diamond. The latter is used to create blocks for Propel and provide design capabilities at the logic level.
Many processor-based motor control solutions exist, but Lattice’s approach is more efficient. It is also possible to manage more and more varied motors with an FPGA.
The reference design provided as part of Lattice Automate uses only one CNN accelerator per chip. It also supports TensorFlow Lite. Support for data collection is also part of the game.